Precompression: A Prelude to Cache Compression

Processors face steep penalties when accessing on-chip memory in the form of high latency. On-chip caches help mitigate this latency by storing the most used data close to the processor. Despite this, cache space limitations limit their effectiveness. Compressing data in caches can improve performance by increasing effective cache capacity, but can incur additional access latency. Current cache compression schemes focus on just one granularity | either a single cache line or a small number of contiguous lines. In this thesis, we propose Precompression a novel technique that transforms cache data, making it more amenable to compression. In contrast to prior compression techniques, our work takes advantage of the redundancy existing across multiple cache lines, stored anywhere in the cache. Precompression works by exploiting the similarity between cache lines to improve compression. For applications within the SPEC2006 and Polybench suites, we observe improvements to the effective compression ratio of up to 13.33%.M.A.S