FPGA library based design of a hardware model for convolutional neural network with automated weight compression using K-means clustering

In this paper, a design of a synthesizable hardware model for a Convolutional Neural Network (CNN) is presented. The hardware model is capable of self-training i.e. without the use of any external processors. It is trained to recognize four numerical digit images. Another hardware model is also designed for the K-means clustering algorithm. This second hardware model is used to for compressing the weights of the CNN through quantization. Weight compression is carried out through weight sharing. With weight sharing, the system is able to save component usage. The two hardware models designed are then subsequently integrated to automate the compression of the CNN weights after the CNN completes its training. The entire design is based on fixed point arithmetic operation using VHDL as design entry tool and XILINX Virtex 5 FPGA as the target library for synthesis. After completing the design, it is evaluated in terms of hardware consumption with respect to rate of compression. When evaluating the recognition performance ability of the hardware model, digit images experimentation results have shown that the weight compression can reach as high as 60% without any negative effect on the performance of the CNN. Based on data gathered, the compression with the least hardware consumption occurs at 80 %. For the various digits trained, the CNN outputs after the training, range from 89% to 97%. © 2019, World Academy of Research in Science and Engineering. All rights reserved