Compiler-assisted compaction/restoration of SIMD instructions

All the supercomputers in the world exploit data-level parallelism (DLP), for example by using single instructions to operate over several data elements. Improving vector processing is therefore key for exascale computing. Control flow divergence is one of the main vector performance limiting factors. Most modern vector instruction sets rely on predication to support divergence control. Nevertheless, the performance and energy consumption in predicated codes is usually insensitive to the number of active elements. Since the trend is that vector register size doubles every four years, the energy efficiency of exascale systems will become sub-optimal. This paper proposes the Compiler-Assisted Compaction/Restoration (CACR) technique. The baseline CR delays predicated SIMD instructions with inactive elements and compacts active elements with instances of the same instruction from later loop iterations to form and execute an equivalent dense vector instruction. The compiler assisted CR analyzes the code looking for key information required to configure CR. Then, it passes this information to the processor via new instructions. Our evaluation shows that CACR improves performance by up to 29\% and reduces dynamic energy consumption by up to 24.2\% on average. The baseline CR only achieves 18.6\% performance and 14\% energy improvements for the same configuration.This work has been partially supported by the Spanish Government (SEV2015-0493, BES-2017-080635), the Spanish Ministry of Science and Innovation (PID2019-107255GBC21/AEI/10.13039/501100011033, RTI2018-098156-B-C53), the ECHO and RoMoL ERC projects (819134, 321253), the European HiPEAC Network and the Mont-Blanc 2020 project (EU-FP7-610402 and EU-H2020-779877). and the Spanish Ministry of Economy, Industry and Competitiveness (RYC-2016-21104, RYC-2017-23269 and RYC-2018-025200-I).Peer ReviewedPostprint (author's final draft