Energy efficient high bandwidth DRAM for throughput processors

Graphics Processing Units (GPUs) and other throughput processing architectures have scaled performance through simultaneous improvements in compute capability and aggregate memory bandwidth. Satisfying the increasing bandwidth demands of future systems without a significant increase in the power budget for the DRAM is a key challenge going forward. A new DRAM architecture, Fine-Grained DRAM, significantly reduces the energy consumption by partitioning the DRAM die into many small independent units, called grains, each of which has a local I/O link to the processor. With this architecture, the on-DRAM data movement energy is greatly reduced due to the much shorter wiring distance between the cell array and the local I/O. At the same time, the energy on the link between the DRAM and GPU remains low by leveraging novel energy-efficient encoding techniques well-suited to the narrow buses. Furthermore, wasteful row overfetch energy due to sparse accesses to large DRAM rows is significantly reduced by reducing the effective DRAM row size in an area efficient manner. This Fine-Grained DRAM architecture enables future reliable, multi-TB/sec memory systems within a power budget comparable to current GPU memory systems.Electrical and Computer Engineerin