Hardware synthesis for systems of recurrence equations with multidimensional schedule

International audienceThis paper introduces methods for extending the classical systolic synthesis methodology to multi-dimensional time which implies the use of memories in the resulting architecture. Memory functions are used to define where the data are stored during execution, the targeted architecture is a distributed memory VLSI circuit. We describe a structural VHDL program for the matrix multiplication algorithm synthesised for a FPGA platform using these design principles. Our results show that the complexity added in each processor by the memories and the control is moderate and justifies in practice the use of such architectures