Add to ORKGThe stuck fault detection efficiency of the test vectors developed for the MIL-M-38510/470 NASA was measured using a hardware stuck fault simulator for the 1802 microprocessor. Thirty-nine stuck faults were not detected out of a total of 874 injected into the combinatorial and sequential parts of the microprocessor. Since undetected faults can create catastrophic errors in equipment designed for high reliability applications, it is recommended that the MIL-M-38510/470 NASA be enhanced with additional test vectors so as to achieve 100% stuck fault detection efficiency
Chip-level modeling techniques in the evaluation of fault tolerant systems were researched. A fault ...
Methods of modeling the detection time or latency period of a hardware fault in a digital system are...
The attitude control electronics mechanization study to develop a fault tolerant autonomous concept ...
Accurate fault models are required to conduct the experiments defined in validation methodologies fo...
A powerful technique particularly appropriate for the detection of errors caused by transient faults...
A set of building block circuits is described which can be used with commercially available micropro...
Modular design techniques improve methods of error detection, diagnosis, and recovery. Theoretical c...
This study describes an experimental analysis of the impact of gate and device-level faults in the p...
This report surveys the field of diagnosis and introduces some of the key algorithms and heuristics ...
In a previous study, Guo, Merrill and Duyar, 1990, reported a conceptual development of a fault dete...
Current research toward real time fault diagnosis for propulsion systems at NASA-Lewis is described....
A methodology for the design of a tightly coupled, highly reliable microprocessor based computer sys...
The paper introduces FTAPE (Fault Tolerance And Performance Evaluator), a tool that can be used to c...
An algorithm was developed which detects, isolates, and accommodates sensor failures using analytica...
The description and specifications for a digital avionics design and reliability analyzer are given....
Chip-level modeling techniques in the evaluation of fault tolerant systems were researched. A fault ...
Methods of modeling the detection time or latency period of a hardware fault in a digital system are...
The attitude control electronics mechanization study to develop a fault tolerant autonomous concept ...
Accurate fault models are required to conduct the experiments defined in validation methodologies fo...
A powerful technique particularly appropriate for the detection of errors caused by transient faults...
A set of building block circuits is described which can be used with commercially available micropro...
Modular design techniques improve methods of error detection, diagnosis, and recovery. Theoretical c...
This study describes an experimental analysis of the impact of gate and device-level faults in the p...
This report surveys the field of diagnosis and introduces some of the key algorithms and heuristics ...
In a previous study, Guo, Merrill and Duyar, 1990, reported a conceptual development of a fault dete...
Current research toward real time fault diagnosis for propulsion systems at NASA-Lewis is described....
A methodology for the design of a tightly coupled, highly reliable microprocessor based computer sys...
The paper introduces FTAPE (Fault Tolerance And Performance Evaluator), a tool that can be used to c...
An algorithm was developed which detects, isolates, and accommodates sensor failures using analytica...
The description and specifications for a digital avionics design and reliability analyzer are given....
Chip-level modeling techniques in the evaluation of fault tolerant systems were researched. A fault ...
Methods of modeling the detection time or latency period of a hardware fault in a digital system are...
The attitude control electronics mechanization study to develop a fault tolerant autonomous concept ...