Add to ORKGThe parallel approach to speeding up simulation is studied, specifically the simulation of digital LSI MOS circuitry on the Intel iPSC/2 hypercube. The simulation algorithm is based on RSIM, an event driven switch-level simulator that incorporates a linear transistor model for simulating digital MOS circuits. Parallel processing techniques based on the concepts of Virtual Time and rollback are utilized so that portions of the circuit may be simulated on separate processors, in parallel for as large an increase in speed as possible. A partitioning algorithm is also developed in order to subdivide the circuit for parallel processing
Distributing simulations among multiple processors is one approach to reducing VHDL simulation time ...
Digital circuit simulation often requires a large amount of computation, resulting in long run times...
Logic simulation is a crucial verification task in processor design. Aiming at significant accelerat...
Parallelization of logic simulation on register-transfer and gate level is a promising way to accele...
With traditional event list techniques, evaluating a detailed discrete event simulation model can of...
Circuit Simulation is a critical bottleneck in VLSI design. This paper describes a parallel switch-l...
This paper presents the results of an experimental study to evaluate the effectiveness of parallel s...
Parallelization of logic simulation on register-transfer and gate level is a promising way to accele...
Simulation has become indispensable in the process of designing, verifying, and testing complex digi...
Simulation has become indispensable in the process of designing, verifying, and testing complex digi...
[[abstract]]Circuit simulation is a very time-consuming and numerically intensive application, espec...
Multi-core architectures are becoming more common and core counts continue to increase. There are s...
In the era of multi-core computing, the push for creating true parallel applications that can run on...
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer S...
As a consequence of Moore's law, the size of integrated circuits has grown extensively, resulting in...
Distributing simulations among multiple processors is one approach to reducing VHDL simulation time ...
Digital circuit simulation often requires a large amount of computation, resulting in long run times...
Logic simulation is a crucial verification task in processor design. Aiming at significant accelerat...
Parallelization of logic simulation on register-transfer and gate level is a promising way to accele...
With traditional event list techniques, evaluating a detailed discrete event simulation model can of...
Circuit Simulation is a critical bottleneck in VLSI design. This paper describes a parallel switch-l...
This paper presents the results of an experimental study to evaluate the effectiveness of parallel s...
Parallelization of logic simulation on register-transfer and gate level is a promising way to accele...
Simulation has become indispensable in the process of designing, verifying, and testing complex digi...
Simulation has become indispensable in the process of designing, verifying, and testing complex digi...
[[abstract]]Circuit simulation is a very time-consuming and numerically intensive application, espec...
Multi-core architectures are becoming more common and core counts continue to increase. There are s...
In the era of multi-core computing, the push for creating true parallel applications that can run on...
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer S...
As a consequence of Moore's law, the size of integrated circuits has grown extensively, resulting in...
Distributing simulations among multiple processors is one approach to reducing VHDL simulation time ...
Digital circuit simulation often requires a large amount of computation, resulting in long run times...
Logic simulation is a crucial verification task in processor design. Aiming at significant accelerat...