Design and modeling of mixed synchronous-asynchronous and hardware-software systems

This thesis presents the design of a hardware/software co-simulator and a case study in the comparison of synchronous and asynchronous design styles of digital VLSI circuits. Adopting the design pattern approach of software design, our simulator software package, based on PtolemyII, extracts the temporal causality of software in embedded systems to perform fast timing estimation of functionality partitioning of hardware/software in embedded systems. Our package can simulate system features such as task prioritization, message passing, resource sharing and task blocking. We demonstrate the proposed approach by two event-driven software applications. In this thesis we also discuss synchronous and asynchronous design styles of VLSI circuits. We use a CDMA correlator to illustrate the different aspects of these design styles. The comparison is presented in terms of area and power. Meanwhile, we also include a switching activity study for the evaluation of architecture tradeoffs