Fast Hardware-Software Co-simulation Using VHDL Models

We describe a technique for hardwaresoftware co-simulation that is almost cycle-accurate, and does not require the use of interprocess communication nor a C language interface for the software components. Software is modeled by using behavioral VHDL constructs, annotated with timing information derived from basic blocklevel timing estimates. Hardware is also modeled in VHDL, and can be either pre-existing Intellectual Property or synthesized to RTL from a functional specification. Execution of the VHDL processes modeling software tasks is coordinated by a process emulatingthe target RTOS behavior. The effects of changing the hardware/software partition can be quickly estimated by changing a process parameter defining its target implementationand the processor on which it is running.