FPGA Based Arbiter Physical Unclonable Function Implementation with Reduced Hardware Overhead

Ivaniuk, A. A.
Zalivaka, S. S.

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Publication date

January 2019

DOI

10.1007/978-3-030-35430-5_18.

Publisher

Springer, Switzerland

Abstract

The paper presents a new architecture of symmetric paths of the arbiter PUF, providing efficient use of the hardware resources of LUT blocks for various Xilinx Artix-7 FPGA family

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FPGA Based Arbiter Physical Unclonable Function Implementation with Reduced Hardware Overhead

Abstract

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FPGA Based Arbiter Physical Unclonable Function Implementation with Reduced Hardware Overhead

Abstract

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