Enhanced physical unclonable function structures in mixed-signal MOS technology

Physical Unclonable Functions (PUFs) present a promising concept for cryptographic hardware. PUFs provide a challenge-response scheme, where the response is not calculated but determined by a kind of randomness available in the device. Every PUF behaves different, even equally manufactured ones. The Arbiter PUF makes use of race conditions between equally designed delay paths. Although the basic principle is proven to work, it suffers from predictability attacks and a not negligible quantity of unreproducible response bits. This thesis deals with the simulation and enhancement of Arbiter PUFs in CMOS technology. A novel simulation approach is introduced, which allows a reliable prediction of the Arbiter PUF"s reproducibility behavior without a transistor level simulation of the whole system. Only the components need to be characterized by circuit simulations using industrial manufacturer models. The resulting PUF can be modeled on a higher level and simulated very fast using statistical distributions. Furthermore the influence of some design parameters on each component"s characteristic is investigated. An enhanced parameter set is determined and evaluated using the new simulation approach. Finally the results are verified by transient transistor level simulations for the reference and the enhanced Arbiter PUF. The bit error rate could be reduced by 61 percent just by design parameter modifications of specific transistors