The Effect of Nanometer-Scale Technologies on the Cache Size Selection for Low Energy Embedded Systems

Several studies have shown that cache memories account for more than 40% of the total energy consumed in processor-based embedded systems. In microscale technology nodes, active power is the primary contributor to the total power dissipation of a CMOS chip. However, in nano-scale technologies, leakage power is dominating total power dissipation. In this paper, we show that this fact affects the optimal cache size for low energy embedded systems. We study a number of embedded applications in three different technologies: 180nm, 100nm and 70nm. The results confirm that for a given application, the optimal cache size for minimal energy consumption varies with the technology. Our study further reveals that the change in the optimal size of cache depends on the rate at which cache misses increase when reducing the cache size; when this rate is sharp, the optimal point is the same for all three technologies, however at less steep rates, smaller caches consume the least energy (upto 91% less energy with only 14% performance loss). Consequently in future nanometer processes, unlike previous technologies, cache size should be minimized to obtain the least energy