www.ijstr.org A new Method for Optimizing Energy Efficiency of Embedded Systems

Abstract Several studies have shown that about 40 % or more of the energy consumption on embedded systems that are based on microprocessor relates to cache. In technology with micrometer scaling, dynamic power was the primary contributor to total power dissipation of a CMOS design, but in technology with nanometer scaling, the share of leakage power in total Power consumption of energy continues to grow. In this paper we concentrate on the selection of optimal cache size for low energy consumption embedded systems. Our study is based on three different technologies on embedded systems. Results show that cache size should change for minimizing energy consumption in different technologies due to the increase of leakage power and decrease of dynamic energy as technology is shrinking. Our studies reveal that cache size changes depend on the rate at which cache miss increases when reducing the cache size. Our experiments show that through technology-aware cache configuration selection, we can reduce the energy consumption by 54 % in average and maximum 75%