A Functional-Level Simulator for the Configurable (Many-Core) PRAM-Like REPLICA Architecture

This master's thesis discusses the design and implementation of a simulator for the REPLICA architecture, a many-core PRAM-like machine. REPLICA provides a programming model that seemingly cannot be provided by mainstream hardware without significant slowdown compared to traditional models. This also implies that it is difficult to simulate REPLICA's programming model on mainstream hardware. Simulator design decisions are described and the resulting simulator is evaluated and compared to existing simulators, where we see that the simulator presented in this thesis is the fastest of them. As seen from the discussion focus in the thesis, most efforts were directed towards simulator execution speed rather than user-facing features