A statistical design approach for a digitally programmable mismatch-tolerant high-speed nauta structure differential OTA in 65-nm CMOS

The Nauta structure differential operational transconductance amplifier (OTA) is introduced as a solution to an amplifier design in deep submicrometer CMOS. This simple high-speed inverter-based architecture uses a negative conductance dc gain enhancement technique to produce high dc gains and large unity gain frequencies. The design tradeoff is that the achievable dc gain is proportional to transistor device matching. Our analysis shows that fixed width Nauta structure OTAs have low dc gains due to variations, and thus viable Nauta OTAs need to have tuning mechanisms available to correct for mismatch. This paper presents a digitally programmable Nauta structure OTA architecture built using digital-to-transconductance converters (DTCs). These DTCs are designed to allow for flexibility in producing digital tuning solutions to the device mismatch problem using Nauta OTAs. We present a theoretical analysis of the digital Nauta OTA solution space for high dc gains and a statistical framework to estimate the likelihood of achieving certain gain specifications. Experimental results from a 65-nm CMOS prototype shows that the architecture achieves an average dc gain of greater than 60 dB in line with the minimum expected gain of 59 dB, and on-chip unity gain bandwidth is inferred above 5.8 GHz