A Statistical Design Framework for Positive-Feedback Gain-Enhancement Operational Transconductance Amplifier Structures In Deep Submicron CMOS.

Ever smaller CMOS process nodes require analog circuit designs that can overcome the many challenges of scaling down into the nanometre CMOS regime – the decreasing voltage supply, shrinking voltage headroom, decreasing intrinsic gain, and the fundamental bandwidth-power-accuracy relation. The positive-feedback gain-enhancement amplifier design using digitally assisted techniques is a promising architecture to solve these issues. One can be implemented by a digitally programmable Nauta structure differential operational transconductance amplifier (OTA) in a simple, single stage, high speed inverter-based architecture using a negative conductance dc gain-enhancement technique to produce high dc gains and large unity gain frequencies.We present a theoretical analysis of the digital Nauta OTA solution for high dc gains and a statistical framework to estimate the likelihood of achieving certain gain specifications. We introduce two architectural variants of a digitally programmable Nauta OTA – one using non-monotonic digital-to-transconductance (DTC) components, and another with a split architecture consisting of fixed width and variable width transconductors utilising the minimum grid-spacing of the CMOS process. A variation-aware statistical design practice is introduced to analyse the sizing of transconductors, computing code-word solutions for statistically likely solutions, and estimating average maximum dc gain over the entire code-space of many simulated OTAs. Prototypes of a 8-bit differential OTA in 180 nm CMOS designed using the fixed and variable width architecture achieves an average maximum dc gain of 60 dB, simulated unity gain frequency of 4.6 GHz, and a figure of merit of 1.0 GHz/mW. Experimental results from a prototype 60-bit differential OTA in 65 nm CMOS using non-monotonic DTCs shows that the architecture achieves an average dc gain of greater than 60 dB, unity gain bandwidth is inferred above 5.8 GHz and a figure of merit of 0.21 GHz/mW.These digitally assisted analog amplifiers are able to overcome the bandwidth-power-accuracy relationships that constrain conventional analog circuits and are viable alternative architectures for increased integration in deep sub-micron CMOS