Area Efficient Device Optimization for ESD Protection in High Speed Interface ICs

Electrostatic discharge (ESD) protection is considered as a vital step in integrated circuit (IC) manufacturing process. IC chips are unable to overcome the effects of transient events without adequate discharge protection. Recent trend in the industry has seen the incorporation of system level ESD protection within the IC chip. Incorporating system level on-chip ESD protection often increases cost, degrades circuit performance and consumes layout area which could otherwise be used for improving the circuit performance. These design challenges could be easily overcome if the parasitic components in a circuit were used for ESD protection. Despite the various design challenges, on-chip ESD protection is still desirable as it saves the area on the circuit board by eliminating the traditional ESD protection devices resulting in more compact circuits. Furthermore, using parasitic components while designing on-chip system level ESD protection can save layout area. In order to effectively implement this solution, a study on ESD events, protection circuits and high-speed ICs was carried out. Different types of ESD events and the different models pertaining to ESD events were studied and are discussed in detail. An overview of high-speed integrated circuits was also carried out with emphasis on the protection topologies that are commonly used. The ESD characteristics of parasitic PNP devices in rail-based ESD protection structure was then studied to summarize its viability as a protection circuit. The turn-on or breakdown voltage of the parasitic PNP is studied by technology computer aided design (TCAD) simulations performed in Silvaco software. The breakdown voltage, holding voltage, on resistance and failure current were studied and modeled to maximize ESD protection