Design of a flexible cryptographic hardware module

The research presented in this thesis focuses on the design of a flexible cryptographic hardware module capable of implementing a variety of private-key cryptographic algorithms and their modes of operation using different implementation methodologies such as iteration and pipelining. The design of the SHERIF cryptographic hardware module was motivated by the difficulties inherent in implementing cryptographic algorithms: software implementation is easy and flexible, but offers low performance, whereas hardware implementations offer high performance but are difficult to design and are generally inflexible. -- The design of the SHERIF architecture was driven by an analysis of several leading block ciphers and hash functions which identified six basic operations that could be used to implement most block ciphers and hash functions. Configurable components were developed to implement each of those operations, and these components were arranged into processing elements capable of implementing a single round of most of the algorithms under consideration. These processing elements were then integrated into a top-level system with complex data control mechanisms to provide added flexibility. -- A sample pipelined implementation of the AES algorithm Rijndael has been successfully simulated. Synthesis results in 0.18 μm CMOS technology suggest the device would have an area of approximately 10 million gates and have a clock speed of 4.78 MHz, leading to a throughput of 611.84 Mbps for the sample implementation of Rijndael. These results demonstrate the flexibility and performance of the system. -- The current SHERIF architecture offers greater flexibility and ease of use than existing cryptographic hardware modules, but there are still many areas in which it can be improved through future research. A number of avenues of future research have been identified that will improve system speed, integration, and flexibility