A PYNQ evaluation platform for FPGA architectures of the Line Hough Transform

The Line Hough Transform (LHT) is an effective line detection algorithm for digital images. To meet real-time requirements, Field Programmable Gate Arrays (FPGAs) are often chosen to accelerate the LHT. However, many LHT architectures select different design parameters and discretisation steps for the Hough Parameter Space (HPS). The work presented in this paper describes a novel evaluation platform for FPGA architectures of the LHT. Our system is named the Hough Evaluation Platform (HEP) and can be used to visualise and inspect the HPS produced from LHT architectures that use different design parameters. Architectures are compared by evaluating the HPS using a unique measurement named the Peak to Mean Vote Ratio (PMVR). Our system employs the PYNQ framework on a Xilinx Zynq MPSoC device for the visualisation of the HPS and also determines the processing time of a given LHT architecture. The HEP has been implemented on a XCZU7EV-2e device and can operate up to a target frequency of 250 MHz