Design and testing on novel non-imprinting SRAM

The security of data information is the most concemmg parameter for memory devices design contemporarily. Many protective actions or mechanisms are implemented to enhance the robustness of the memory against the externally unauthorised access. Tamper response apparatus is the most prevailing measure which erases the whole stored data instantly in case of any detected threat. However, due to the transistor's intrinsic electrical characteristics, all the memories especially non-volatile memory like SRAM severely suffers from the imprinting effect and leaves the high risk of data stolen. The conventional countermeasures are susceptible to both physical and non-invasive attacks. In addition, high area consumption and power overhead are also inevitable deficiencies of these designs. Because SRAM are commonly used to store the sensitive, secret or confidential data in practice, the novel 22-T SRAM architecture are introduced and tested in this thesis. The designed SRAM effectuates bit flipping operation during stand-by mode individually so as to balance the charge strength at each transistor's gate. Moreover, the reset circuit is also included in cell structure in order to realize high speed erasure. The lKB SRAM chip is operating at 1.2V supply voltage at 25°C and final fabricated on GF 65nm technology. The details around the testing flow design are also elaborated in this thesis.Master of Science (Integrated Circuit Design