Design techniques for improving SRAM Cell Stability in Advanced Technology

As CMOS technology continuously scales, the process variability becomes a major challenge in designing large-sized memories. Random threshold voltage variations due to dopant fluctuations, line edge roughness and poly gate grain size variations have been shown to significantly reduce the DC read, write and retention margins of CMOS SRAM cells [1-2]. These random local variations have shown to be also influenced by systematic variations across chip, wafer and lot. To satisfy the functionality of a large number of SRAM cells in memory and thus achieve high yield, the design has to provide more than 6 standard deviations of margin to parameter variations. This requirement is very stringent in small feature-size CMOS technology with low supply voltage. There have been many reported designs to measure and improve the SRAM cell stability [3]. However, many papers focused on how to improve static stability and there were few papers mentioning the SRAM dynamic stability. In 2006, Khellah et al. [4] addressed the wordline and bitline pulsing schemes to improve SRAM cell failure rates at low voltages in single-Vcc designs. Suzuki et al. [5] described a SRAM with an 8-T SRAM cell that copes with cell disturbances in unselected columns during a write event. In 2007, Khellah et al. [6] presented a method to measure the dynamic SRAM stability degradation due to the power supply noise. We propose design techniques for improving SRAM cell stability in low-voltage, advanced technology. As a base of our work, we will verify the effectiveness of wordline and bitline pulsing schemes in 45nm CMOS technology. By incorporating pulse-generation building blocks, both high-stability of SRAM cell and low power dissipation can be achieved. Also, precise timing control of SRAM control signals will be helpful to improve the SRAM cell stability. Based on these techniques, we will try to find novel schemes to further enhance the dynamic stability of SRAM cell. This will bring us to energy-efficient, variation-tolerant SRAM design compatible with the process scaling