University of Rochester. Department of Electrical and Computer Engineering, 2016.Despite the proliferation of multi-core and multi-threaded architectures, exploiting implicit parallelism for a single semantic thread is still a crucial component in achieving high performance. While a canonical out-of-order engine can effectively uncover implicit parallelism in sequential programs, its effectiveness is often hindered by instruction and data supply imperfections (manifested as branch mispredictions and cache misses). Look-ahead is a tried-and-true strategy to exploit implicit parallelism, but can have resource-inefficient implementations such as in a conventional, monolithic out-of-order core. A more decoupled approach with an independent, de...
We propose a new technique for exploiting the inherent parallelism in lazy functional programs. Know...
Speculative thread-level parallelization is a promising way to speed up codes that compilers fail to...
This paper describes future execution (FE), a simple hardware-only technique to accelerate indi-vidu...
While a canonical out-of-order engine can effectively exploit implicit parallelism in sequential pro...
Thesis (Ph. D.)--University of Rochester. Department of Electrical and Computer Engineering, 2019.Si...
Recent proposals for Chip Multiprocessors (CMPs) advocate speculative, or implicit, threading in whi...
The shift of the microprocessor industry towards multicore architectures has placed a huge burden o...
The era of multi-core processors has begun. These multi- core processors represent a significant shi...
In this paper we present an automated way of using spare CPU resources within a shared memory multi-...
With speculative thread-level parallelization, codes that cannot be fully compiler-analyzed are aggr...
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Comput...
Maximal utilization of cores in multicore architectures is key to realize the potential performance ...
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Comp...
Simultaneous Multithreading (SMT) is proposed to improve pipeline throughput by overlapping executio...
Multi-core and many-core systems are the norm in contemporary processor technology and are expected...
We propose a new technique for exploiting the inherent parallelism in lazy functional programs. Know...
Speculative thread-level parallelization is a promising way to speed up codes that compilers fail to...
This paper describes future execution (FE), a simple hardware-only technique to accelerate indi-vidu...
While a canonical out-of-order engine can effectively exploit implicit parallelism in sequential pro...
Thesis (Ph. D.)--University of Rochester. Department of Electrical and Computer Engineering, 2019.Si...
Recent proposals for Chip Multiprocessors (CMPs) advocate speculative, or implicit, threading in whi...
The shift of the microprocessor industry towards multicore architectures has placed a huge burden o...
The era of multi-core processors has begun. These multi- core processors represent a significant shi...
In this paper we present an automated way of using spare CPU resources within a shared memory multi-...
With speculative thread-level parallelization, codes that cannot be fully compiler-analyzed are aggr...
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Comput...
Maximal utilization of cores in multicore architectures is key to realize the potential performance ...
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Comp...
Simultaneous Multithreading (SMT) is proposed to improve pipeline throughput by overlapping executio...
Multi-core and many-core systems are the norm in contemporary processor technology and are expected...
We propose a new technique for exploiting the inherent parallelism in lazy functional programs. Know...
Speculative thread-level parallelization is a promising way to speed up codes that compilers fail to...
This paper describes future execution (FE), a simple hardware-only technique to accelerate indi-vidu...