Design Of A Decompressor Engine On A Sparc Processor

Code compression, initially conceived as an effective technique to reduce code size in embedded systems, today also brings advantages in terms of performance and energy consumption, due to an increase in the cache hit ratio. This paper proposes the design of a code decompressor engine for our dictionary-based method, embedding it into the Leon (SPARC V8) processor. Our design guarantees that the processor cycle-time is maintained and the decompression is performed on-the-fly. We have achieved a functional implementation on a FPGA1 with compression ratios ranging from 72% to 88%, performance improvement as high as 45% and a reduction on energy consumption reaching 35%, validated through two real-world benchmarks suites: MediaBench and MiBench. We also explore some trade-offs between compression ratio and performance. Copyright 2005 ACM.110114Benini, L., Macii, A., Nannarelli, A., Code compression for cache energy minimization in embedded systems (2002) IEE Proceedings on Computers and Digital Techniques, 149 (4), pp. 157-163. , JulyGaisler, J., Leon2 processor user's manual 1.0.24 (2004), SeptLEON-PCI-XC2V Development Board (2004) User Manual, 6. , Gaisler ResearchGuthaus, M., Ringenberg, J., Ernst, D., Austin, T., Mudge, T., Mibench: A free, commercially representative embedded benchmark suite (2001) Proc. of the IEEE 4th Annual Workshop on Workload Characterization, pp. 3-14. , DecLee, C., Potkonjak, M., Mangione-Smith, W., Mediabench: A tool for evaluating and synthesizing multimedia communication systems (1997) Proc. Int 'I Symp. on Microarchitecture, pp. 330-337. , DecLekatsas, H., Henkel, J., Wolf, W., Code compression for low power embedded system design (2000) Proc. ACM/IEEE Design Automation Conference, pp. 294-299Lekatsas, H., Henkel, J., Wolf, W., Design and simulation of a pipelined decompression architecture for embedded systems (2001) Proc. ACM/IEEE Int'l Symp. on System Synthesis, pp. 63-68. , OctNetto, E.W., Azevedo, R., Centoducatte, P., Araujo, G., Mixed static/dynamic profiling for dictionary based code compression (2003) Proc. of the International Symposium on System-on-Chip, pp. 159-163. , NovNetto, E.W., Azevedo, R., Centoducatte, P., Araujo, G., Multi-profile based code compression (2004) Proc. ACM/IEEE Design Automation Conference, , JuneWolfe, A., Chanin, A., Executing compressed programs on an embedded RISC architecture (1992) Proc. Int'l Symp. on Microarchitecture, pp. 81-91. , No