An analytical mismatch model of nano-CMOS device under impact of intrinsic device variability

We present for the first time an analytical model for the effect of short-gate transistor mismatch on analogue circuit design. Analogue circuit design is very vulnerable to device mismatch, as large numbers of matching-sensitive circuits are used. This is particularly severe in short-gate CMOS processes. In this paper, a new analytical mismatch model is developed for both triode and saturation regimes and verified using 35nm gate-length BSIM4 model cards. Short-channel effects, such as velocity saturation and mobility degradation, are taken into consideration. The results achieved excellent agreement with Monte Carlo HSPICE simulations. Furthermore, this model can be used to develop a rapid estimate of the precision or production yield of a circuit based only on the process statistics