Study of statistical variabilities in nanoscaled MOSFETs

reaching 10nm lateral dimensions, variability in device performance becomes a major issue in the design of integrated circuits. The goal of this work is to characterize and to model the mismatch in MOS transistors at the nanoscale dimension. Silicon technology has now entered the nano-CMOS era with 40 nm MOSFETs in mass production at the current 45 nm technology node [1] and sub-10 nm transistors expecte