LegUp: Open-source High-level Synthesis Research Framework

The rate of increase in computing performance has been slowing due to the end of processor frequency scaling and diminishing returns from multiple cores. We believe the industry is heading towards heterogeneous computing, an accelerator era, where specialized hardware is harnessed for better power efficiency and compute performance. A natural platform for these accelerators are field-programmable gate arrays (FPGAs), which are integrated circuits that can implement large custom digital circuits including complete system-on-chips. However, programming an FPGA can be an arduous undertaking even for experienced hardware engineers. We propose raising the abstraction level by allowing a designer to incrementally move their design from a processor to a set of hardware accelerators, each automatically synthesized from a software implementation. This dissertation describes LegUp, an open-source high-level synthesis (HLS) framework that enables this new design methodology. We further present novel improvements to the quality of the synthesized circuits when targeting FPGAs. First, we present the LegUp high-level synthesis framework with an overview of our design flow. The software is unique among academic tools for offering a wide support of the ANSI C software language, for targeting a hybrid processor/accelerator architecture, and for being open-source. We also show that the quality of results produced by LegUp are competitive with a commercial HLS tool. Next, we present an FPGA architecture-specific HLS resource sharing approach. Our technique multi-pumps high-speed DSP blocks on modern FPGAs by clocking them at twice the system clock frequency. We show that multi-pumping can reduce circuit area without impacting performance. Following this, we describe a novel loop pipeline scheduling algorithm. Our approach handles complex constraints by using a backtracking method to discover better scheduling possibilities. This scheduling algorithm improves throughput for complex loop pipelines compared to prior work and a commercial tool. Finally, we examine LegUp's target memory architecture and describe how to partition memory within the circuit hierarchy using information from compiler alias analysis. We also present a method to efficiently use the block RAMs present in modern FPGAs by grouping memories together. These techniques decrease memory usage and improve performance for our HLS-generated circuits.Ph.D