Efficient Software Checking for Fault Tolerence

As semiconductor technology scales into the deep submicron regime the occurrence of transient or soft errors will increase. This will require new approaches to error detection. Software checking approaches are attractive because they require little hardware modification and can be easily adjusted to fit different reliability and performance requirements. Unfortunately, software checking adds a significant performance overhead. In order to make software checking system more attractive, this dissertation proposes three optimization techniques that reduce the overhead of software error checking approaches. The first technique uses boolean logic to identify code patterns that correspond to outcome tolerant branches. We develop a compiler algorithm that finds those patterns and removes the unnecessary replicas. In the second technique we evaluate the performance benefit obtained by removing address checks before load and stores. In addition, we evaluate the overheads that can be removed when the register file is protected in hardware. The third technique ESoftCheck composes of a set of compiler optimizations to detect and remove "non-vital" checks. ESoftCheck optimizes redundant checks, checks before loop induction variables and invariants and unnecessary checks on platforms where registers are hardware-protected with parity or ECC. ESoftCheck also provides knobs to trade reliability for performance based on the support for recovery and the degree of trustiness of the operations. In the end, this dissertation proposes an interesing future work, which is to find a set of variables protecting which it can most likely catch harmful errors that would cause Silent Data Corruption to the program. By ignoring non-harmful errors, the cost spent on detecting them and unnecessary rollbacks can be saved