In this paper we present a simple analytical model to predict the hit ratio for a direct mapped cache. The hit ratio is defined as the probability that an arbitrary memory request is satisfied from the cache. A simple analytic expression is obtained for calculating the probability. Address traces obtained when programs are executed on a computer, are used to evaluate the probability. Trace driven simulation is used to show that the analytical model predicts the cache hit ratio to within 10%. The main merit of the proposed model is its simplicity, leading to fast prediction of cache hit ratio
. Many scientific applications handle compressed sparse matrices. Cache behavior during the executio...
The cache Miss Ratio Curve (MRC) serves a variety of purposes such as cache partitioning, applicatio...
Because of the infeasibility or expense of large fully-associative caches, cache memories are often ...
This paper describes a model for studying the cache performance of algorithms in a direct-mapped cac...
The standard trace-driven cache simulation evaluates the miss rate of cache C on an address trace T ...
This paper describes a model for studying the cache performance of algorithms in a direct-mapped cac...
Improving cache performance requires understanding cache behavior. However, measuring cache performa...
Improving cache performance requires understanding cache behavior. However, measuring cache performa...
In this work, we study systems with two levels of memory: a fixed-size cache, and a backing store, e...
Sparse matrices are in the kernel of numerical applications. Their compressed storage, which permits...
Cache behavior is complex and inherently unstable, yet it is a critical factor affecting program per...
86 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1988.Trace-driven simulation is a s...
The performance of direct mapped caches is degraded by conflict misses. It has been shown that confl...
The standard trace-driven cache simulation evaluates the miss rate of cache C on an address trace T ...
The performance of direct mapped caches is degraded by conflict misses. It has been shown that confl...
. Many scientific applications handle compressed sparse matrices. Cache behavior during the executio...
The cache Miss Ratio Curve (MRC) serves a variety of purposes such as cache partitioning, applicatio...
Because of the infeasibility or expense of large fully-associative caches, cache memories are often ...
This paper describes a model for studying the cache performance of algorithms in a direct-mapped cac...
The standard trace-driven cache simulation evaluates the miss rate of cache C on an address trace T ...
This paper describes a model for studying the cache performance of algorithms in a direct-mapped cac...
Improving cache performance requires understanding cache behavior. However, measuring cache performa...
Improving cache performance requires understanding cache behavior. However, measuring cache performa...
In this work, we study systems with two levels of memory: a fixed-size cache, and a backing store, e...
Sparse matrices are in the kernel of numerical applications. Their compressed storage, which permits...
Cache behavior is complex and inherently unstable, yet it is a critical factor affecting program per...
86 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1988.Trace-driven simulation is a s...
The performance of direct mapped caches is degraded by conflict misses. It has been shown that confl...
The standard trace-driven cache simulation evaluates the miss rate of cache C on an address trace T ...
The performance of direct mapped caches is degraded by conflict misses. It has been shown that confl...
. Many scientific applications handle compressed sparse matrices. Cache behavior during the executio...
The cache Miss Ratio Curve (MRC) serves a variety of purposes such as cache partitioning, applicatio...
Because of the infeasibility or expense of large fully-associative caches, cache memories are often ...