Expected Values for Cache Miss Rates for a Single Trace (Technical Summary)

The standard trace-driven cache simulation evaluates the miss rate of cache C on an address trace T for program P running on input data I with object-code address map M for P. We note that the measured miss rate depends significantly on the address mapping M set arbitrarily by the compiler and linker. In this paper, we remove the effect of the address-mapping on the miss rate by analyzing a symbolic trace T of basic blocks. By assuming each basic block has an equal probability of ending up anywhere in the cache,\u27we determine the average miss rate over all possible address mappings. We present the gap model for predicting the mean and variance of the miss rate for direct-mapped caches. Our model also predicts how an intervening trace, such as an operating system call or a task switch, will affect the miss rate. For fully-associative caches, we give the expected number of misses for different working set sizes. In particular, for a working set of size w, and a fully-associative cache of size L, the expected number of misses until the working set is resident is = Lln(L/L - w) for w \u3c L. We present a metric for estimating the interference between two parts of a program, which is important in choosing a address mapping that minimizes cache conflicts. Finally, we present a method to compactly summarize a trace that allows accurate miss rate prediction for direct-mapped caches