Hardware Architectures for the Inverse Square Root and the Inverse Functions using Harmonized Parabolic Synthesis

This thesis presents a comparison between implementations of the inverse square root function, using two approximation algorithms; Harmonized Parabolic Synthesis and the Newton-Raphson Method. The input is a 15 bit fixed-point number, the range of which is selected so that the implementation is suitable for use as a block implementing the inverse square root for floating-point numbers, and the designs are constrained by the error, which must be < 2^(-15). Multiple implementations of both algorithms have been investigated and simulated as Application-Specific Integrated Circuits using STM 65.0nm Complementary Metal-Oxide Seminconductor technology libraries for Low Power and General Purpose, VDD levels of 1.00V and 1.10V, and for various clock speeds. Error distribution, area, speed, power, and energy consumption are analyzed for variants of the implementations of the two algorithms. Depending on how the properties rank in desirability, when choosing an implementation, the recommended choice will vary. The thesis finds that if mean error, and error distribution are important, the implementations of Harmonized Parabolic Synthesis show superiority regarding implementable clock speed, area requirements, power and energy consumption. If power and energy consumption is the most prioritised property, an implementation of the Newton-Raphson algorithm is promising, although at the cost of a worse error distribution