Mower is a micro-architecture technique which targets the branch misprediction penalty in superscalar processors. It speeds-up the misprediction recovery process by dynamically evicting stale instructions and correcting the Register Alias Table (RAT) using explicit control dependency tracking. Tracking control dependencies is accomplished by using simple bit matrices. This low-overhead technique allows overlapping of the recovery process with instruction fetching, renaming and scheduling from the correct path. Our evaluation of the mechanism indicates that it yields performance very close to ideal recovery and provides up to 5% speed-up and 2% reduction in power consumption compared to a recovery mechanism using a reorder buffer and a walke...
Conventional CAD methodologies optimize a processor module for correct operation and prohibit timing...
Abstract. Modern processors use speculative execution to improve performance. However, speculative e...
Current processors exploit out-of-order execution and branch prediction to improve instruction level...
Mower is a micro-architecture technique which targets branch misprediction penalties in superscalar ...
Current trends in modern out-of-order processors involve imple-menting deeper pipelines and a large ...
Current trends in modern out-of-order processors involve implementing deeper pipelines and a large i...
Superscalar processors take advantage of speculative execution to improve performance. When the spec...
This paper presents the concept of dynamic control independence (DCI) and shows how it can be detect...
Conventional CAD methodologies optimize a processor module for correct operation, and prohibit timin...
Conventional computer-aided design (CAD) methodologies optimize a processor module for correct opera...
Pipelined microprocessors allow the simultaneous execution of several machine instructions at a time...
Modern superscalar processors highly rely on the speculative execution which speculatively executes ...
To alleviate the memory wall problem, current architectural trends suggest implementing large instru...
This paper evaluates several mechanisms for repair-ing the return-address stack after branch mispred...
Though current general-purpose processors have several small CPU cores as opposed to a single more c...
Conventional CAD methodologies optimize a processor module for correct operation and prohibit timing...
Abstract. Modern processors use speculative execution to improve performance. However, speculative e...
Current processors exploit out-of-order execution and branch prediction to improve instruction level...
Mower is a micro-architecture technique which targets branch misprediction penalties in superscalar ...
Current trends in modern out-of-order processors involve imple-menting deeper pipelines and a large ...
Current trends in modern out-of-order processors involve implementing deeper pipelines and a large i...
Superscalar processors take advantage of speculative execution to improve performance. When the spec...
This paper presents the concept of dynamic control independence (DCI) and shows how it can be detect...
Conventional CAD methodologies optimize a processor module for correct operation, and prohibit timin...
Conventional computer-aided design (CAD) methodologies optimize a processor module for correct opera...
Pipelined microprocessors allow the simultaneous execution of several machine instructions at a time...
Modern superscalar processors highly rely on the speculative execution which speculatively executes ...
To alleviate the memory wall problem, current architectural trends suggest implementing large instru...
This paper evaluates several mechanisms for repair-ing the return-address stack after branch mispred...
Though current general-purpose processors have several small CPU cores as opposed to a single more c...
Conventional CAD methodologies optimize a processor module for correct operation and prohibit timing...
Abstract. Modern processors use speculative execution to improve performance. However, speculative e...
Current processors exploit out-of-order execution and branch prediction to improve instruction level...