FPGA Implementation of a Pseudo-Chaotic Number Generator and Evaluation of its Performance

International audienceNowadays, chaos-based cryptographicprimitives are used as an alternative to classicalcryptographic primitives for data security. Indeed, thisis because the fact that there is intrinsic randomnessin chaotic signals and ease of designing robust chaosbasedcryptographic primitives. A common andimportant element in chaos-based cryptography isthe Pseudo-Chaotic Number Generator (PCNG).A variety of PCNG with software implementationhas been published in the literature. However, dueto the rapid growth of Internet of Things (IoT),it is necessary to have such primitive in hardwareimplementation such as an FPGA. In this paper weaddress the hardware implementation on SAKURA-GFPGA-board using VHDL, of one of our PCNGs thatwas designed, implemented in C code and analyzed.We realized also the implementation in Matlab,for approving our hardware implementation. Theperformance of the hardware implementation in termsof statistical tests, throughput and logic resources iscompared with some other PCNGs