An asynchronous floating point unit

technical reportAn asynchronous floating point unit (FPU) was designed using application specific integrated circuit (ASIC) and very large scale integration (VLSI) technologies. The FPU is capable of adding, subtracting, multiplying, and dividing single-precision format numbers as defined by The Institute of Electrical and Electronics Engineers (IEEE). An addition or subtraction can execute in parallel with a multiplication or division. The FPU uses two phase handshaking with bundled data paths. It uses iterative serial-parallel algorithms for multiplication and division and a straight forward addition and subtraction algorithm.; The FPU was created from a range of technologies. The controller, multiplication, and division circuits use field programmable gate arrays (FPGAs). The addition and subtraction circuits are implemented with a 2.0 pum complementary metal oxide silicon (CMOS) chip.; The FPU was interfaced to an Atari ST computer for testing. Under this platform, multiplication and division were measured at 10.5 thousand floating point operations per second (KFLOPS) and addition and subtraction at 13.6 KFLOPS. The "linpack" benchmark program rates the FPU at 8 KFLOPS. Additionally, the hardware was tested with automatic test equipment. Under this platform, the multiplication hardware was measured at 20.0 KFLOPS, division at 15.4 KFLOPS, and addition and subtraction at; 256. 4 KFLOPS