Enhancing the L1 Data Cache Design to Mitigate HCI

© 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.[EN] Over the lifetime of a microprocessor, the Hot Carrier Injection (HCI) phenomenon degrades the threshold voltage, which causes slower transistor switching and eventually results in timing violations and faulty operation. This effect appears when the memory cell contents flip from logic '0' to '1' and vice versa. In caches, the majority of cell flips are concentrated into only a few of the total memory cells that make up each data word. In addition, other researchers have noted that zero is the most commonly-stored data value in a cache, and have taken advantage of this behavior to propose data compression and power reduction techniques. Contrary to these works, we use this information to extend the lifetime of the caches by introducing two microarchitectural techniques that spread and reduce the number of flips across the first-level (L1) data cache cells. Experimental results show that, compared to the conventional approach, the proposed mechanisms reduce the highest cell flip peak up to 65.8 percent, whereas the threshold voltage degradation savings range from 32.0 to 79.9 percent depending on the application.This work has been supported by the Spanish Ministerio de Economia y Competitividad (MINECO), by FEDER funds through Grant TIN2012-38341-C04-01, by the Intel Early Career Faculty Honor Program Award, by a HiPEAC Collaboration Grant funded by the FP7 HiPEAC Network of Excellence under grant agreement 287759, and by the Engineering and Physical Sciences Research Council (EPSRC) through Grants EP/K026399/1 and EP/J016284/1. Additional data related to this publication are available in the data repository at https://www.repository.cam.ac.uk/handle/1810/249006.Valero Bresó, A.; Miralaei, N.; Petit Martí, SV.; Sahuquillo Borrás, J.; Jones, TM. (2016). Enhancing the L1 Data Cache Design to Mitigate HCI. IEEE Computer Architecture Letters. 15(2):93-96. https://doi.org/10.1109/LCA.2015.2460736939615