Effects of Processor Parameter Selection on Simulation Results

Due to cost, time, and flexibility constraints, simulators are needed to explore the design space when developing a new processor architecture as well as when evaluating the performance of new compiler-based and microarchitectural mechanisms. However, improperly choosing the processor parameters, such as the cache size, the associativity, the number of functional units, and so forth, can significantly affect the simulation results, independent of any new mechanism being evaluated. As a first step in developing a methodology to appropriately choose the processor parameters to be used in a simulation, we quantify the effect of a select group of ten key parameters on the total execution time (measured in simulated cycles) using the statistical analysis of variance (ANOVA) technique. Our results show that, for the commonly used SimpleScalar simulator, the number of reorder buffer entries, the L1 D-Cache associativity and size, and the memory latency account for approximately 75 % of the total observed variation in the execution time. Conversely, the branch predictor has surprisingly little effect, only about 1%. In addition, we find that interactions between parameters also have little effect on the total execution time. This work clearly demonstrates that poor choices of simulated processor parameter values, or even a single poor choice, can significantly affect the simulation results and thereby lead to erroneous conclusions about the processor or mechanism being simulated.