Statistical simulation of multithreaded architectures

Detailed, cycle-accurate processor simulation is an inte-gral component of the design and study of computer archi-tectures. However, as the detail of simulation and processor design size increase, simulation times grow exponentially, and it becomes increasingly necessary to find fast, efficient simulation techniques that still ensure accurate results. At the same time, multithreaded multi-core designs are in-creasingly common, and require increased experimental de-sign evaluation for a number of reasons including higher system complexity, interaction of multiple co-scheduled ap-plication threads, and workload selection. Although several effective simulation techniques exist for single-threaded ar-chitectures, techniques have not been effectively applied to the simulation of multithreaded and multi-core architecture models. Moreover, multithreaded processor simulation in-troduces unique challenges in all simulation stages. This work introduces systematic extensions of commonly-used statistical simulation techniques to multithreaded systems. The contributions of this work include: tailoring simulation fast-forwarding for individual threads, the effects of cache warming on application threads, and an analysis of the pri-mary issues of efficient multithreaded simulation.