The current many-core architectures are generally evaluated by a detailed emulation with a cycle-accurate simulation of the execution time. However this detailed simulation of the architecture makes the evaluation of large programs very slow. Since the focus in many-core architecture is shifting from the performance of the individual core to the overall behavior of chip, high-level simulations are becoming neces- sary, which evaluate the same architecture at less detailed level and allow the designer to make quick and reasonably accurate design decisions. We have developed a high-level simulator for the design space exploration of the Microgrid, which is a many-core architecture comprised of many fine- grained multi-threaded cores. This sim...
In recent years, the research focus has moved from core microarchitecture to uncore microarchitectur...
Increased complexity of micro-electronic systems demands a need for efficient system level models. S...
Traditional processors use the von Neumann execution model, some other processors in the past have u...
The Microgrid is a many-core architecture comprising multiple clusters of fine-grained multi-threade...
As the complexity of processors increases, it becomes harder for designers to understand the non-tri...
The design and evaluation of microprocessor architectures is a difficult and time-consuming task. Al...
Detailed, cycle-accurate processor simulation is an inte-gral component of the design and study of c...
Future integrated systems will contain billions of transistors, composing tens to hundreds of IP cor...
Simulation is an important means of evaluating new microarchitectures. With the invention of multi-c...
Multi-core processors are everywhere now, researchers all over the world are finding ways to benchm...
In hardware/software codesign, Discrete Event Simulation (DES) has been in use for decades to verify...
The trend to develop increasingly more intelligent systems leads directly to a considerable demand f...
Architectural simulation is time-consuming, and the trend towards hundreds of cores is making sequen...
In this paper we present MCoreSim, an open-source simulation framework for massively parallel and ma...
Multithreaded architectures are widely used for, among other things, hiding long memory latency. In ...
In recent years, the research focus has moved from core microarchitecture to uncore microarchitectur...
Increased complexity of micro-electronic systems demands a need for efficient system level models. S...
Traditional processors use the von Neumann execution model, some other processors in the past have u...
The Microgrid is a many-core architecture comprising multiple clusters of fine-grained multi-threade...
As the complexity of processors increases, it becomes harder for designers to understand the non-tri...
The design and evaluation of microprocessor architectures is a difficult and time-consuming task. Al...
Detailed, cycle-accurate processor simulation is an inte-gral component of the design and study of c...
Future integrated systems will contain billions of transistors, composing tens to hundreds of IP cor...
Simulation is an important means of evaluating new microarchitectures. With the invention of multi-c...
Multi-core processors are everywhere now, researchers all over the world are finding ways to benchm...
In hardware/software codesign, Discrete Event Simulation (DES) has been in use for decades to verify...
The trend to develop increasingly more intelligent systems leads directly to a considerable demand f...
Architectural simulation is time-consuming, and the trend towards hundreds of cores is making sequen...
In this paper we present MCoreSim, an open-source simulation framework for massively parallel and ma...
Multithreaded architectures are widely used for, among other things, hiding long memory latency. In ...
In recent years, the research focus has moved from core microarchitecture to uncore microarchitectur...
Increased complexity of micro-electronic systems demands a need for efficient system level models. S...
Traditional processors use the von Neumann execution model, some other processors in the past have u...