L0 buffer energy optimization through scheduling and exploration

Clustered L0 buffers are an interesting alternative to reduce energy consumption in the instruction memory hierarchy of embedded VLIW processors. Currently, the synthesis of L0 clusters is performed as a hardware optimization, where the compiler generates a schedule and based on the given schedule L0 clusters are generated. However, the cluster synthesis is sensitive to the given schedule. This offers an interesting design space to explore the effects on clustering by altering the schedule to increase energy efficiency. In this paper we present a preliminary study indicating the potentials offered by scheduling for L0 clusters in terms of L0 buffer energy reduction. A list scheduler is extended to recognize the L0 clusters and based on a few simple heuristics operations are assigned to clusters. An iterative methodology is employed to explore the design space. The simulation results indicate that up to 10 % of L0 buffer energy can potentially be reduced by scheduling for L0 clusters with a simple heuristic. 1