Combining cooperative software/hardware prefetching and cache replacement

Data prefetching is an effective technique to hide memory latency and thus bridge the increasing processor-memory performance gap. Our previous work presents guided region prefetching (GRP), a hardware/software cooperative prefetching technique which cost-effectively tolerates L2 latencies. The compiler hints improve L2 prefetching accuracy and reduce bus bandwidth consumption compared to hardware only prefetching. However, some useless prefetches remain to degrade memory performance. This paper first explores a more aggressive GRP prefetching scheme which pushes L2 prefetches into the L1, similar to the IBM Power 4 and 5 cache designs. This approach yields some additional performance improvements. This work then combines GRP with evict-me, a compilerassisted cache replacement policy. This combination can reduce cache pollution introduced by useless prefetches and further improve memory system performance.