Add to ORKGAbstract. This paper outlines a formal model of the Intel IA-64 architecture, and explains how this model can be used to verify the correctness of assembly-level code optimizations. The formalization and proofs were carried out using the HOL Light theorem prover.
We describe a technique for automatically proving compiler optimizations sound, meaning that their t...
Abstract—We consider the impact of compiler optimizations on the quality of high-level synthesis (HL...
This thesis describes novel techniques and test implementations for optimizing numerically intensive...
) Ramayya Kumar, Thomas Kropf, Klaus Schneider University of Karlsruhe, Institute of Computer Design...
this paper, a verification method is presented which combines the advantages of deduction style proo...
For the past decade, a framework combining model checking (symbolic trajectory evaluation) and highe...
This thesis explores building provably correct software and hardware inside the HOL4 interactive the...
In this paper, we describe formal modelling of the digital signal processors of the family ADSP-2100...
This paper presents a fully verified interactive theorem prover for higher-order logic, more specifi...
Theorem proving allows the formal verification of the correctness of very large systems. In order to...
The use of Higher-Order Languages as a programming tool tends to reduce the development cost of Soft...
We present a Coq-based system to certify the entire process of implementing declarative mathematical...
This thesis is about verified computer-aided checking of mathematical proofs. We build on tools for ...
The aim of this thesis is to investigate the integration of hardware description lamguaages (HDLs) a...
. In this article we present a structured approach to formal hardware verification by modelling circ...
We describe a technique for automatically proving compiler optimizations sound, meaning that their t...
Abstract—We consider the impact of compiler optimizations on the quality of high-level synthesis (HL...
This thesis describes novel techniques and test implementations for optimizing numerically intensive...
) Ramayya Kumar, Thomas Kropf, Klaus Schneider University of Karlsruhe, Institute of Computer Design...
this paper, a verification method is presented which combines the advantages of deduction style proo...
For the past decade, a framework combining model checking (symbolic trajectory evaluation) and highe...
This thesis explores building provably correct software and hardware inside the HOL4 interactive the...
In this paper, we describe formal modelling of the digital signal processors of the family ADSP-2100...
This paper presents a fully verified interactive theorem prover for higher-order logic, more specifi...
Theorem proving allows the formal verification of the correctness of very large systems. In order to...
The use of Higher-Order Languages as a programming tool tends to reduce the development cost of Soft...
We present a Coq-based system to certify the entire process of implementing declarative mathematical...
This thesis is about verified computer-aided checking of mathematical proofs. We build on tools for ...
The aim of this thesis is to investigate the integration of hardware description lamguaages (HDLs) a...
. In this article we present a structured approach to formal hardware verification by modelling circ...
We describe a technique for automatically proving compiler optimizations sound, meaning that their t...
Abstract—We consider the impact of compiler optimizations on the quality of high-level synthesis (HL...
This thesis describes novel techniques and test implementations for optimizing numerically intensive...