Add to ORKGIn this paper, we describe formal modelling of the digital signal processors of the family ADSP-2100 using the HOL (Higher Order Logic) theorem prover. While specifying the behavior and implementation of the processor, we solved the problem of complexity related to the large number of parameters by using a structured method based on our knowledge about the processor architecture. We show details of the specification strategy used and display few illustrative examples
Abstract Real-time systems usually involve a subtle interaction of a number of dis-tributed componen...
Abstract. This chapter describes our work on formal verification of floating-point algorithms using ...
AbstractWhen a digital filter is realized with floating-point or fixed-point arithmetics, errors and...
In this thesis we propose a framework for the incorporation of formal methods in the design flow of ...
This paper proposes a framework for the incorporation of formal methods in the design flow of digita...
Deep datapath and algorithm complexity have made the verification of floating-point units a very har...
this thesis we formally specify and verify an implementation of the Orthogonal Frequency Division Mu...
Ascertaining correctness of digital hardware designs through simulation does not scale-up for large ...
The IEEE-754 oating-point standard, used in nearly all oating-point applications, is consid-ered one...
) Ramayya Kumar, Thomas Kropf, Klaus Schneider University of Karlsruhe, Institute of Computer Design...
Nowadays, the formal verification of hardware is gaining a lot of importance in the design flow of m...
In this paper, we introduce a novel approach for high level synthesis for DSP algorithms. Two featur...
this paper, a verification method is presented which combines the advantages of deduction style proo...
Abstract. This paper outlines a formal model of the Intel IA-64 architecture, and explains how this ...
As a result of enormous competition in the system-on-chip industry, the current trends of system lev...
Abstract Real-time systems usually involve a subtle interaction of a number of dis-tributed componen...
Abstract. This chapter describes our work on formal verification of floating-point algorithms using ...
AbstractWhen a digital filter is realized with floating-point or fixed-point arithmetics, errors and...
In this thesis we propose a framework for the incorporation of formal methods in the design flow of ...
This paper proposes a framework for the incorporation of formal methods in the design flow of digita...
Deep datapath and algorithm complexity have made the verification of floating-point units a very har...
this thesis we formally specify and verify an implementation of the Orthogonal Frequency Division Mu...
Ascertaining correctness of digital hardware designs through simulation does not scale-up for large ...
The IEEE-754 oating-point standard, used in nearly all oating-point applications, is consid-ered one...
) Ramayya Kumar, Thomas Kropf, Klaus Schneider University of Karlsruhe, Institute of Computer Design...
Nowadays, the formal verification of hardware is gaining a lot of importance in the design flow of m...
In this paper, we introduce a novel approach for high level synthesis for DSP algorithms. Two featur...
this paper, a verification method is presented which combines the advantages of deduction style proo...
Abstract. This paper outlines a formal model of the Intel IA-64 architecture, and explains how this ...
As a result of enormous competition in the system-on-chip industry, the current trends of system lev...
Abstract Real-time systems usually involve a subtle interaction of a number of dis-tributed componen...
Abstract. This chapter describes our work on formal verification of floating-point algorithms using ...
AbstractWhen a digital filter is realized with floating-point or fixed-point arithmetics, errors and...