Bypass Aware Instruction Scheduling for

Since register files suffer from some of the highest power densities within processors, designers have investigated several architectural strategies for register file power reduction, including “On Demand RF Read ” where the register file is read only if the operand value is not available from the bypasses. However, we show in this paper that significant additional reductions in the register file power consumption can be obtained by scheduling instructions so that they transfer the operands via bypasses, rather than reading from the register file. Such instruction scheduling requires the compiler to be cognizant of the bypasses in the processor pipeline. In this paper, we develop several bypass aware instruction scheduling heuristics varying in time complexity, and study their effectiveness on the Intel XScale processor pipeline running MiBench benchmarks. Our experimental results show additional power consumption reductions of up to 26 % and on average 12 % over and above the register file power reduction achieved through existing techniques