Memory coherence activity prediction in commercial workloads

for the degree of Master of Science. Recent research indicates that prediction-based coherence optimizations offer substantial performance improvements for scientific applications in distributed shared memory multiprocessors. Important commercial applications also show sensitivity to coherence latency, which will become more acute in the future as technology scales. Together, these observations suggest the importance of investigating coher-ence activity prediction in the context of commercial workloads. This thesis studies a trace-based Downgrade Predictor (DGP) for predicting last stores to shared cache blocks prior to consumption by other processors, and a pattern-based Consumer Set Predictor (CSP) for predicting subsequent readers. We evaluate this class of predictors on commercial applications and demon-strate that our DGP correctly predicts 51%-94 % of last stores. Memory sharing patterns in commercial workloads are inherently non-repetitive; hence CSP cannot predict a significant fraction of consumers. We develop an improved DGP design by extending our trace-based DGP to exploit multiple underlying predic-tion tables, and demonstrate this hierarchical predictor accurately predicts 63%-97 % of last stores on commercial workloads