Robust Codes for Fault Attack Resistant Cryptographic Hardware

Abstract. Hardware implementations of cryptographic algorithms are vulnerable to fault analysis attacks. To detect these attacks we propose an architecture based on robust nonlinear systematic (n,k)-error-detecting codes. These nonlinear codes offer advantages over linear codes since they are capable of providing uniform error detecting coverage independently of the error distributions. They make no assumptions about what faults or errors will be injected by an attacker. Architectures based on these codes have fewer undetectable errors than linear codes with the same (n,k). We also present several optimization approaches which provide for a tradeoff between the levels of robustness and required overhead for hardware implementations.