Taylor Expansion Diagram (TED) is a compact, wordlevel, canonical representation for data flow computations that can be expressed as multi-variate polynomials. TEDs are based on a decomposition scheme using Taylor series expansion that allows to model word-level signals as algebraic symbols. This power of abstraction, combined with canonicity and compactness of TED, makes it applicable to equivalence verification of dataflow designs. The paper describes the theory of TEDs and proves their canonicity. It shows how to construct a TED from a HDL design specification and discusses application of TEDs in proving equivalence of such designs. Experiments were performed with a variety of designs to observe the potential and limitations of TEDs for ...
We describe a data structure and a set of BDD based algorithms for efficient formal design verificat...
Designers use a variety of notations, some of them diagrammatic, while developing systems. Unfortuna...
Abstract Exponential computational complexity of digital systems formal verification algorithms excl...
Abstract—A Taylor Expansion Diagram (TED) is a compact, word-level, canonical representation for dat...
International audienceThis paper presents a new, compact, canonical graph-based representation, call...
International audienceAn original technique to transform functional representation of the design int...
12 pagesInternational audienceThis paper describes a systematic method and an experimental software ...
An original technique to transform functional representation of the design into a structural represe...
Abstract – Formal verification of complex digital systems requires a mechanism for efficient represe...
This thesis extends the work and application of Taylor Expansion Diagrams (TED) as a framework for h...
International audienceThis paper describes a systematic method and an experimental software system f...
Optimization of designs specified at higher levels of abstraction than gate-level or register-transf...
Formal verification has become one of the most important steps in circuit design. In this context th...
dence Flow Graphs topic affiliation: System-level Synthesis (06-04), System-level verification (06-...
Abstract. In this paper we give a short overview of the decision diagrams, and define a special clas...
We describe a data structure and a set of BDD based algorithms for efficient formal design verificat...
Designers use a variety of notations, some of them diagrammatic, while developing systems. Unfortuna...
Abstract Exponential computational complexity of digital systems formal verification algorithms excl...
Abstract—A Taylor Expansion Diagram (TED) is a compact, word-level, canonical representation for dat...
International audienceThis paper presents a new, compact, canonical graph-based representation, call...
International audienceAn original technique to transform functional representation of the design int...
12 pagesInternational audienceThis paper describes a systematic method and an experimental software ...
An original technique to transform functional representation of the design into a structural represe...
Abstract – Formal verification of complex digital systems requires a mechanism for efficient represe...
This thesis extends the work and application of Taylor Expansion Diagrams (TED) as a framework for h...
International audienceThis paper describes a systematic method and an experimental software system f...
Optimization of designs specified at higher levels of abstraction than gate-level or register-transf...
Formal verification has become one of the most important steps in circuit design. In this context th...
dence Flow Graphs topic affiliation: System-level Synthesis (06-04), System-level verification (06-...
Abstract. In this paper we give a short overview of the decision diagrams, and define a special clas...
We describe a data structure and a set of BDD based algorithms for efficient formal design verificat...
Designers use a variety of notations, some of them diagrammatic, while developing systems. Unfortuna...
Abstract Exponential computational complexity of digital systems formal verification algorithms excl...