Optimization of designs specified at higher levels of abstraction than gate-level or register-transfer level (RTL) has been shown to have the greatest impact on the quality of synthesized hardware. This work presents a systematic method and an experimental software system for behavioral transformations of designs specified at algorithmic and behavioral levels. It targets data-flow and computation-intensive designs used in digital signal processing applications. The system is intended to provide transformations of the initial design specifications prior to architectural and RTL synthesis. It aims at optimizing practical designs while taking into consideration hardware design constraints. The system is based on canonical, graph-based represen...
The number of incremental and iterative steps in the digital IC design & automation methodology will...
High Level Synthesis (HLS) is a process which, starting from a high-level description of an applicat...
By allowing higher-level descriptions, behavioral synthesis helps to cope with the growing chips\u27...
12 pagesInternational audienceThis paper describes a systematic method and an experimental software ...
An original technique to transform functional representation of the design into a structural represe...
International audienceThis paper describes a systematic method and an experimental software system f...
This thesis extends the work and application of Taylor Expansion Diagrams (TED) as a framework for h...
International audienceAn original technique to transform functional representation of the design int...
TDS is an experimental software system to perform high-level transformations of designs specified at...
The first step in high level synthesis consists of translating a behavioral specification into its c...
Behavioral synthesis takes an algorithmic description of the circuit where there is neither clock in...
As the complexity of integrated circuit systems increases, automated hardware design from higher-lev...
As a result of enormous competition in the system-on-chip industry, the current trends of system lev...
Manual optimization of Register Transfer Level (RTL) datapath is commonplace in industry but holds b...
This paper analyzes the reasons why behavioral synthesis was never widely accepted by designers, and...
The number of incremental and iterative steps in the digital IC design & automation methodology will...
High Level Synthesis (HLS) is a process which, starting from a high-level description of an applicat...
By allowing higher-level descriptions, behavioral synthesis helps to cope with the growing chips\u27...
12 pagesInternational audienceThis paper describes a systematic method and an experimental software ...
An original technique to transform functional representation of the design into a structural represe...
International audienceThis paper describes a systematic method and an experimental software system f...
This thesis extends the work and application of Taylor Expansion Diagrams (TED) as a framework for h...
International audienceAn original technique to transform functional representation of the design int...
TDS is an experimental software system to perform high-level transformations of designs specified at...
The first step in high level synthesis consists of translating a behavioral specification into its c...
Behavioral synthesis takes an algorithmic description of the circuit where there is neither clock in...
As the complexity of integrated circuit systems increases, automated hardware design from higher-lev...
As a result of enormous competition in the system-on-chip industry, the current trends of system lev...
Manual optimization of Register Transfer Level (RTL) datapath is commonplace in industry but holds b...
This paper analyzes the reasons why behavioral synthesis was never widely accepted by designers, and...
The number of incremental and iterative steps in the digital IC design & automation methodology will...
High Level Synthesis (HLS) is a process which, starting from a high-level description of an applicat...
By allowing higher-level descriptions, behavioral synthesis helps to cope with the growing chips\u27...