Caches are partitioned intosubarrays for optimal timing. In a set-associative cache, if the way holding the data is known before anaccess, only subarrays for that way need tobe accessed. Reduction in cache switching activities results in energy savings. In this paper, we propose to extend the branch prediction framework to enable wayfootprint prediction. The next fetch address and its way-footprint are predicted simultaneously for one-way instruction cache access. Because the way-footprint prediction shares some prediction hardware with the branch prediction, additional hardware cost is small. To enlarge the number of one-way cache accesses, we have made modi cations to the branch prediction. Speci cally, we have investigated three BTBalloc...
International audienceLong pipelines need good branch predictors to keep the pipeline running. Curre...
During the 1990s Two-level Adaptive Branch Predictors were developed to meet the requirement for acc...
In the pursuit of instruction-level parallelism, significant demands are placed on a processor's ins...
SUMMARY Energy consumption has become an important design consideration in modern processors. Theref...
Fetching instructions from a set-associative cache in an embedded processor can consume a large amou...
A sequence of branch instructions in the dynamic instruction stream forms a branch sequence if at mo...
Processor architectures will increasingly rely on issuing multiple instructions to make full use of ...
Set-associative caches achieve low miss rates for typical applications but result in significant ene...
With the increasing performance gap between the processor and the memory, the importance of caches i...
This paper proposes a low-energy solution for CAM-based highly associative I-caches using a segmente...
A method for reducing the power consumption of set-associative caches is proposed. The method tracks...
[[abstract]]Focusing on the way-predicting cache with sub-block placement, we propose a new cache sc...
Abstract—Energy efficiency plays a crucial role in the design of embedded processors especially for ...
In this paper we propose Instruction-based Prediction as a means to optimize directory-based cache c...
This paper describes a new on-demand wakeup prediction policy for instruction cache leakage control ...
International audienceLong pipelines need good branch predictors to keep the pipeline running. Curre...
During the 1990s Two-level Adaptive Branch Predictors were developed to meet the requirement for acc...
In the pursuit of instruction-level parallelism, significant demands are placed on a processor's ins...
SUMMARY Energy consumption has become an important design consideration in modern processors. Theref...
Fetching instructions from a set-associative cache in an embedded processor can consume a large amou...
A sequence of branch instructions in the dynamic instruction stream forms a branch sequence if at mo...
Processor architectures will increasingly rely on issuing multiple instructions to make full use of ...
Set-associative caches achieve low miss rates for typical applications but result in significant ene...
With the increasing performance gap between the processor and the memory, the importance of caches i...
This paper proposes a low-energy solution for CAM-based highly associative I-caches using a segmente...
A method for reducing the power consumption of set-associative caches is proposed. The method tracks...
[[abstract]]Focusing on the way-predicting cache with sub-block placement, we propose a new cache sc...
Abstract—Energy efficiency plays a crucial role in the design of embedded processors especially for ...
In this paper we propose Instruction-based Prediction as a means to optimize directory-based cache c...
This paper describes a new on-demand wakeup prediction policy for instruction cache leakage control ...
International audienceLong pipelines need good branch predictors to keep the pipeline running. Curre...
During the 1990s Two-level Adaptive Branch Predictors were developed to meet the requirement for acc...
In the pursuit of instruction-level parallelism, significant demands are placed on a processor's ins...