Exploring Efficient SMT Branch Predictor Design

Abstract: Branch prediction in simultaneous multithreaded processors is difficult because multiple independent threads interfere with shared prediction resources. We evaluate the prediction accuracy of four branch predictor configurations: 1) a totally shared predictor, 2) a completely split predictor, 3) a predictor with a shared history and split BHT, and 4) a predictor with a shared BHT and separate history registers, each for two static prediction schemes, a generic 2-bit predictor, a Gshare predictor, and a YAGS predictor. We simulate each combination listed with four threads executing a different benchmark and with each thread executing the same code. We conclude that for an execution with unique threads, separating the branch history register for each thread allows for higher prediction accuracy by eliminating the negative aliasing between threads. Surprisingly, this splitting of predictor resources still performs better than a shared predictor even when each thread is running the same code. This study demonstrates that allotting each thread its own history register to access a shared predictor table gives performance close to that of a totally split predictor while using significantly less resources. Overall system performance, as measured in CPI, is only marginally affected by branch prediction accuracy in a multithreaded environment because threadlevel parallelism allows for the hiding of long latency hazards, such as branch mispredicts. As such, we feel that branch prediction accuracy is not of peak importance when running multithreaded applications and that valuable development time and chip resources should be spent on other issues