An Effective Bypass Mechanism to Enhance Branch Predictor for SMT Processors

Abstract. Unlike traditional superscalar processors, Simultaneous Mul-tithreaded processor can explore both instruction level parallelism and thread level parallelism at the same time. With a same fetch width, SMT fetches instructions from a single thread not so deeply as in tra-ditional superscalar processor. Meanwhile, all the instructions from dif-ferent threads share the same Function Unites in SMT. All the charac-teristics make it possible to enhance the performance of SMT through reducing the branch mis-prediction. Based on the fact that about 15% of branch instructions whose directions can be definitely known at pre-dicting cycle, a simple and effective bypass mechanism is proposed. This scheme doesn’t depend on any existed branch predictor, and can be used as an effective enhancement to them. Execution-driven simulation results show that the branch prediction miss rates of our predictor decrease by more than 15 % on average compared with a simple base line (g-share) predictor and improve the instruction throughput by about 2.5%.