Selective Dual Path Execution (SDPE) reduces branch misprediction penalties by selectively forking a second path and executing instructions from both paths following a conditional branch instruction. SDPE restricts the number of simultaneously executed paths to two, and uses a branch prediction confidence mechanism to fork selectively only for branches that are more likely to be mispredicted. A branch forking policy defines the behavior of SDPE when a low confidence branch prediction is encountered while two paths are already being executed. Trace driven simulation is used to evaluate the effectiveness of SDPE with three different forking policies. SDPE can reduce the cycles lost to branch mispredictions by 34 to 50%, resulting in an approx...
textPerformance of modern pipelined processor depends on steady flow of useful instructions for proc...
Commodity microprocessors uniformly apply branch prediction and single path speculative execution to...
Pipelining is a major technique used in high performance processors. But a fundamental drawback of p...
This work presents a hybrid branch predictor scheme that uses a limited form of dual path execution ...
Even sophisticated branch-prediction techniques necessarily suffer some mispredictions, and even rel...
In the present computer architecture, speculation execution is the general and effective way to hand...
Pipeline stalls due to branches represent one of the most significant impediments to realizing the p...
Accurate branch prediction can be seen as a mechanism for enabling design decisions. When short pipe...
Though current general-purpose processors have several small CPU cores as opposed to a single more c...
The goal of this Thesis is reducing the global penalty associated to branch mispredictions, in terms...
In this paper, we examined the behavior of three of the best performing branch prediction strategies...
In simultaneous multithreaded architectures many separate threads are running concurrently, sharing ...
Predicated execution has been used to reduce the number of branch mispredictions by eliminating hard...
Computers are everywhere and the need for always more computation power has pushed the processor arc...
There is wide agreement that one of the most important impediments to the performance of current and...
textPerformance of modern pipelined processor depends on steady flow of useful instructions for proc...
Commodity microprocessors uniformly apply branch prediction and single path speculative execution to...
Pipelining is a major technique used in high performance processors. But a fundamental drawback of p...
This work presents a hybrid branch predictor scheme that uses a limited form of dual path execution ...
Even sophisticated branch-prediction techniques necessarily suffer some mispredictions, and even rel...
In the present computer architecture, speculation execution is the general and effective way to hand...
Pipeline stalls due to branches represent one of the most significant impediments to realizing the p...
Accurate branch prediction can be seen as a mechanism for enabling design decisions. When short pipe...
Though current general-purpose processors have several small CPU cores as opposed to a single more c...
The goal of this Thesis is reducing the global penalty associated to branch mispredictions, in terms...
In this paper, we examined the behavior of three of the best performing branch prediction strategies...
In simultaneous multithreaded architectures many separate threads are running concurrently, sharing ...
Predicated execution has been used to reduce the number of branch mispredictions by eliminating hard...
Computers are everywhere and the need for always more computation power has pushed the processor arc...
There is wide agreement that one of the most important impediments to the performance of current and...
textPerformance of modern pipelined processor depends on steady flow of useful instructions for proc...
Commodity microprocessors uniformly apply branch prediction and single path speculative execution to...
Pipelining is a major technique used in high performance processors. But a fundamental drawback of p...